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What's in a name?

By:David K. Every
©Copyright 1999

IA64 is Intels implementation of RISC. I know that Intel doesn't want to call it RISC -- they want to imply that it something revolutionary and give it a NEW name like "EPIC". For the past few years they have been squirming when it was called RISC or VLIW-like (but admit that it is a VLIW processor).

RISC (Reduced Instruction Set Computing) is the concept of reducing an instruction sets' complexity (modernizing your instruction sets' design) so that you can use the gates (extra space) for things that make the instructions go faster with techniques like adding cache (fast memory), pipelining (breaking the instructions down into sub parts, and preprocessing as much as possible), superscalar (executing instructions in parallel), a load-store architecture (the computer can either load or store, and not try to do many things or both in the same instruction), adding more registers, and adding bits that can help with things like branch-prediction and other things -- all to make the machine faster.

VLIW (Very-Long Instruction-Word) is a form of RISC, where you can "group" RISC instructions into a bigger "word" -- so big it called a Very-Long Instruction Word -- then it executes all the instructions in parallel. It is still a TYPE of RISC processor -- but it is a unique type. Like Dogs are Mammals -- VLIW is usually a RISC chip.

EPIC (Explicit Parallel Instruction Computing) is a form of VLIW, and RISC, with a few additions. Basically, it uses VLIW instructions, but has some "hints" embedded in the instruction set to help with the parallelism and to reduce branching (with predication), and it has a few more registers, and some other minor changes. It is still a TYPE of RISC processor, and a type of VLIW processor. Like Collies are Dogs, and Dogs are Mammals -- EPIC is VLIW, and VLIW is RISC.

What's the difference?

The difference between RISC and VLIW is the instruction parallelism. In RISC you use "Superscalar" to load lots of single instructions, and the processor executes them in parallel (at the same time) -- all decoding (reordering, etc.) is done by the chip.

In VLIW you load "groups" of instructions at the same time (and try to execute them in parallel) -- so the compiler can optimize for those groups to increase performance (a tad) over plain RISC. All these instructions together make one long instruction word (group) -- but the individuals instructions are usually just RISC instructions. VLIW's problem is that it is not scalable (easily upgradable). Say you are loading 4 x RISC instructions at the same time, then you want to improve the processor. With VLIW if you try to scale it up to read 6 instructions at a time, it is not an even divisor of 4 -- all the old code is designed for groupings of 4. So a 6 instruction VLIW processor could actually be slower that a 4 instruction version on older code (it wouldn't align right). Not only that, there are cases where the code just doesn't sequence right to use all groupings correctly -- so only 1, 2 or 3 of the 4 instructions in that group get used (the others are wasted). This causes code creep (wasted area), and also wastes potential performance.

EPIC is a an attempt to fix some of the problems of normal VLIW, and add some other more modern RISC tricks (like Predication) to do more in parallel.

RISC does the parallelism as well -- but the compiler doesn't have to optimize (specialize) the code (as much). This means a little more responsibility is on the hardware (processor), and code is less dependant on the implementation -- compared to VLIW, it is harder to say how EPIC will fare in the real world.

About time

10 years after the rest of the industry has moved to RISC, along comes Intel. They create a totally new Chip (or swear they will any year now). This new Chip will have a new instruction set called IA64 (catchy, isn't it). The first version of the Chip is code named "Merced", and will offer reasonable performance (compared to other RISC chips of the time) -- but Intel promises that two years after the original they are planning a chip that will DOUBLE performance ("ohhh, aaah"). Of course according to Moore's Law says that transistors should double every 18 months (and does so in the rest of the industry) -- which roughly translates to a doubling in performance. So according to Intel's schedule they are going to fall behind the normal development curve -- but so far no one in the press has mentioned this observation, instead they gobble up Intels press release as some "revolution".

Ironically, Merced is slipping so far behind schedule, that now it is only one year after Merced ships the follow-on (called McKinley) should ship, and double performance. And it might slip as far as "the same time" by the time things are finished slipping. Of course that isn't a reflection on Intel doing something good (by doubling performance in a short time) but more a reflection on the poor job at shipping Merced and IA64 on time. Merced was originally scheduled for '97 -- and here we are, it has slipped a few times, and now '00 is the year... really, this time they mean it. I expect it December 32nd.

What does IA64 do? It is fully catch-phrase compliant, and forces everyone to follow Intels lead again. By changing the instruction set, Intel can force the Chip Cloners to respond to them. Great for Intel -- questionable for the industry (depending on how good their implementation is). The real thing IA64 does is to finally modernize Intels chip design from the x86 (Pentiums) -- a register starved processor architecture that is still firmly planted in it's 1970's origins -- to a more modern instruction set.

How did Intel modernize the instruction set?

  1. They added more registers (lots of them) -- like RISC.
  2. They simplified the instructions set complexity -- like RISC.
  3. They added a load-store architecture -- like RISC.
  4. They increase the cache -- like RISC.
  5. They increased the pipelining -- like RISC.
  6. They added bits for optimizing branch prediction and the like -- like RISC.

Sound like RISC so far? That is because it is!

Intel also borrowed a little from VLIW.

  1. They decided to group instructions into long words -- like VLIW

VLIW (Parallel RISC) is not a proven technology, and there are still serious questions about it in the real world -- it requires highly specialized compilers to achieve performance beyond ordinary RISC -- and even then, it has only been used successfully in very specialized task (like multi-media processing, graphics, sound, or tasks that can be easily broken into parallel segments). We are, as of yet, unsure how well it can perform in the real world (as compared to regular RISC).

Now Intel has decided to try to fix the problems with VLIW in a few ways. They added more bits for decoding register groupings, and added a lot more registers. These are attempts to allow the processor to be more scalable than other VLIW implementations (and hide the problems with VLIW). Intel has enough smart people that they will probably pull it off, and have a chip that is a fast RISC-VLIW-EPIC processor. They will also probably take over the compiler market, because it will cost many millions of dollars (and years of effort) to make a compiler complex enough that can work with this processor type efficiently.


Intel was forced to go with VLIW for a reason -- they need to be able to run older x86 programs. The easiest way to do this, is to have a small part of the chip, that can read the old complex x86 instruction and expand it (decode it) into a series of RISC instructions that do the same thing as the older single instruction (this group seems to fit the VLIW / EPIC mold). This will allow for an on-chip emulator (converter) to run old code, and it is easiest to do if you can convert one instruction into a group of instructions (all contained in one very-long instruction word).

If this sounds a bit kludgy, it is. What it does is it brings much of the baggage (and many of the extra gates and wasted space) of a CISC implementation -- and it slaps that on top of that a newer (cleaner) RISC implementation. So it is better (than what Intel had) -- but not the best RISC design possible. Intel still has to waste space, which could otherwise be using to make the RISC/VLIW part of the processor go even, to run the old CISC (x86) translation stuff. Fortunately, this on-chip emulator will be a pretty small part of the chip -- so it shouldn't be too much of a penalty in the real world. The kludge will allow the processor to do two separate tasks (run old x86 tasks, and new highly optimized and fast ones).


What we must remember in all this, is while EPIC and IA64 are probably a reasonable evolution of RISC and VLIW, it is still BOTH. VLIW is parallel RISC. IA64 (EPIC) is VLIW with some specialty bits and more registers and a few tweaks. IA64 is still a RISC processor, and it is still a VLIW processor -- only the name has changed (to protect the guilty).

Intel has a long history of selling things that make their life easier, as some revolution. MMX is a way to lock people into a more Intel proprietary instruction set. It does add a little value, but it was nothing new. Some people claimed it was a "revolution" even though that functionality (SIMD) existed for decades before Intel copied it. In reality MMX was just the poorest SIMD / Vector Unit ever to grace a shipping processor. Now they are doing the same with EPIC which is RISC/VLIW repackaged as something new, with a few minor tweaks, as a way for Intel to gain market share -- and some are pretending that it is something revolutionary.

EPIC is a nice evolution (for Intel). It will probably be a very nice performing RISC chip -- and I expect that it will be 20 - 30% faster than other RISC chips (best case). Intel has the money and name to make it work -- so it should not be ignored or discounted. But it is no more a revolution than a car company adding a few more colors, or increasing their horsepower. They tweaked and modified (and added more registers) -- but we will have to wait for a few more years before we find out how much horsepower that will really add.

Created: 11/20/97
Revised: 04/09/99
Updated: 11/09/02

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