615 - IBM's PowerPC + x86
Originally scheduled for late '96 and slipped into '97, this processor was supposed to run both PowerPC and x86 code native. This is speculation based on leaks out of IBM's R&D. No official announcements or specifications ever came from IBM. All numbers presented are highly uncertain.
There were two basic directions of this rumor.
The common rumor was that IBM was working on an x86 core that they would incorporate with the PowerPC core, and share as much hardware as possible. This would be more like two processors on a single chip. This rumor diverged on whether it was targeted at x86 customers to offer them fast PowerPC instructions -- or whether it was targeted at PowerPC customers to allow x86 emulation. Depending on which of those, depended on what the pinouts would be and who's socket the chip would plug into. The more likely rumor being the chip would plug into x86 sockets. There was also conflicting rumors as to whether the chip would require a reboot to switch "modes" (to go from x86 to PPC mode).
The other rumor, that was less common, was that IBM was going to actually hardware decode (emulate) the x86 instruction set more in PowerPC's hardware, similar to what Intel is likely to do with Merced (expand the instruction set from x86 to native, similar to software emulators only faster because there isn't as many load penalties and other limited support for endian translation, registers, and so on).
I imagine both paths were at least briefly explored which lead to the conflicting rumors (or there was intentional conflicting leaks to confuse things). I suspect that the latter design was dropped for the former (early in the process), but then after some experimentation or market research it was learned that the numbers just couldn't support such a chip. PC vendors wouldn't be that interested in a new "non-Intel" architecture, with no native software -- which seems to be supported by DEC-ALPHA's mediocre acceptance.
It is not that such a chip is impossible (or even that difficult) to do -- it is just that the performance hits or costs may not make it worth while (1). Plus IBM seemed to be falling on their faces around this time, when it came to mainstreaming OS/2 (their likely motivation for the chip). Microsoft started trying to gouge IBM and Motorola for further development of WindowsNT for PowerPC, followed by a resounding thump as IBM and Motorola dropped WindowsNT for PPC in any further plans (killing another motivation for the chip). I also heard that IBM's partial hardware emulation approach would have required support from Microsoft for NT to run -- but Microsoft demanded money from IBM (a lot), so IBM just walked.
An intriguing product died, before it ever really had a chance.
(1) Even going the other way, as a PowerPC customer, I wouldn't want a 20% performance hit on PPC code, even if it meant 50-100% faster x86 emulation. Especially if it meant lots of extra heat, cost, and so on. I imagine the x86 camp feels much the same way. Even if the chip is created, there are big issues of getting hardware to support both platforms designs, and so on.
(2) 64 bits often means how much data is addressed. PowerPC's work with 64 bits+ of data for Floating Point math, Integers are 32 bits in the other PPC's (for now). For data sizes larger than 32 bit ints, it seems that AltiVec (and its 128 bit register) is a better solution.
This monster processor was designed for Server and very high end markets. With 7 Million transistors, 64 bit addressing, and a LOT of heat generation, it was never intended to be used in Macs. The program ran into some bugs and wasn't quite achieving performance -- while the other PowerPC's were exceeding their performance numbers. They released the 620 in small quantities, but it never went into full production.
Then AIM went back into the labs to continue work and redesign (620e?). But again, by the time everything was getting worked out for this "improved" version of the processor, the 604e's were already at 200 MHz+ and performing to within a few percentage points of the 620's at a fraction of the cost (and power). The 620 got refocused again (Motorola seemed especially determined not to give up on this design) -- and again, by the time things started getting closer to delivery, it became obvious that the G3's and Mach5 were close to delivery (and close to the same performance again) -- and they were far cheaper and easier to manufacture.
So the 620 was just too complex to keep up with the rest of the PowerPC product line. Little time delays gave Moore's law enough time to eat any advantages of the 620 away. (Similar to the fate of the x704). The other PowerPC's just kept surpassing their goals by so much, that they made the 620 into a commercial flop even before it got out of the gate. During this time Microsoft tried to gouge Motorola for WindowsNT (for PPC) and delayed versions of NT like people change underwear, so Motorola lost the OS's that could have made the 620 a viable server solution (IBM had already given up on OS/2). So the partners dropped the effort.
There have been some 620's sold, but not many -- and those mostly for specialty systems. I believe much of the design work for the 620 got reused in other areas -- like borrowing some cache logic, or branch prediction, and possibly even some parts of the core for the G4's. IBM probably used parts of the 620 design for the 630 or PowerPC/AS (custom versions of the PowerPC used for their AS/400 line).
The clock rate was supposed to compensate for all design tradeoffs (2), and there were quite few. The design was borrow from the older 604 (not the 604e's). They also had to reduced the size of the cache's to get the cost (heat and money) down. This processor also had only one Integer and one Floating point unit (as compared to 2/3 for the 604e), so it couldn't do as much at the same time.
(2) Don't mistakenly try to scale the performance linearly with the clock rates, or apply one processor performance to another. These processors were not as fast at the same clock rate (MHz to MHz) as some of the other PowerPC's.
The problem was that Exponential was not able to keep up with the advancement in CMOS based PowerPC's. Their manufacturing was not able to keep up with IBM and Motorola. It took Exponential 18 months (instead of the estimated 12 months) to bring their product to market. They had targeted 533 MHz for Q1 '97, they were only able to release 410 MHz for production in Q3 '97. They also missed on their development cost budget, their power budget, and their performance goals. IBM and Motorola got the Mach5 (350 MHz 604e) and G3's to market faster and with higher performance than people thought possible. This just made the x704 impractical -- it cost more, it used far more power, it dissipated far more heat, it required special cooling systems, it was going to require code-optimization and OS support, and just didn't perform well enough.
The x704 was getting respectable performance scores compare to other Macs of the time -- but by the time the chip was available in volume and OS support for it was ready (another quarter or two), the chip would be irrelevant.
Theoretically BiPolar could be applied to the G3 design for the next generation of Exponential chip, but if it takes them another 18 months to release their product (which seemed to be the case), then the G4 chips would be coming out, and again the industry would pass them by. So while the BiPolar technology may be viable -- the realities of "time to market", and design lags are keeping Exponential from being viable (3).
(3) If IBM or Motorola used BiPolar, then it may have been viable -- but it does not look like that is going to happen because it is not worth it to them to waste a lot of heat and add design complexity and cost, to get a very small amount of performance gains. It looks like best case the BiPolar could only be 6 months ahead of CMOS designs in performance -- and that is just too narrow of a window.
760 & 770
There were rumors of MP supported G3's being worked on, with support for both a 2 processor or 4 processor MP versions. However, IBM and Motorola also started investigating putting multiple cores (processors) onto a single chip. It also requires OS multiprocessing support to take full advantage of hardware MP. Since Apple wasn't likely to get that done enough until late '98 or early '99, and the G4 was scheduled for around the same time, it seemed like this effort could be focused on the G4.
There was also rumors of a G3 with huge plots of cache -- something like 512K - 1 Meg of 1:1 L1/L2 cache integrated onto the chip (sorta like the first PentiumPro, but on a single chip). This would effect performance in the positive, but would also increase costs, all at the same time Apple was trying to reduce costs on the G3's, so they could create things like the iMac. Plus the backside cache was performing very well indeed, allowing Apple (and others) to selectively add the right amount of cache. So this concept got pushed off until the G4 as well.
So there are a few dead-chips in the PowerPC camp. Some will see those as "failings" and undelivered promises. I find that a little irrational, since in all of these cases there was something else that was filling the roles as good (or better) than the targeted chip was going to anyway. So they were just cases of technology growing too fast, or other extenuating circumstances, obsoleting processors before they got released.